1. Field of the Invention
The present invention relates to an analog memory cell circuit, particularly to an analog memory cell circuit for the low temperature polycrystalline silicon thin film transistor liquid crystal display (LTPS TFT-LCD).
2. Description of the Prior Art
Thin film transistor liquid crystal displays (TFT-LCDs) have become a mainstream of plannar display markets due to its light-weight, thin-thickness and high-contrast-ratio. However, power consumption becomes a serious issue for the TFT-LCDs, especially for the portable products. The research reports mentioned that the power consumption almost comes from the backlight system and AC power supplying to liquid crystal of the source drivers. Therefore, the memory-in-pixel (MIP) concept was proposed to meet low power application, which provided a low power standby mode for continuous display of static images without the power wastage on the source drivers. By refreshing the voltage level of scan lines, polarity inversion could be easily achieved even though the data is no longer furnished.
So far, the literatures were reported with the digital MIP circuits. They can be classified as two basic approaches; the static type and the dynamic type. In general, the static digital MIP circuit exhibits the lowest power consumption since the dynamic power is only consumed while pixels are charged during polarity inversion. However, the main drawback of the static digital MIP is too large in layout area for displaying with a fine pixel pitch. The static MIP circuits typically required seven or eight TFTs and six row lines per pixel. On the contrary, the dynamic digital MIP circuits are more attractive because of fewer TFTs and row lines per pixel.
FIG. 1 shows the conventional dynamic digital MIP circuit. As shown in FIG. 1, the dynamic digital MIP circuit 100 is achieved with three N-type thin film transistors (NTFTs) for one bit operation. The NTFTs comprise the first transistor (M1), the second transistor (M2) and the third transistor (M3). The manipulation starts at pre-charging the data line in the initial stage. During the reading period, the data line voltage can be defined by the gate bias (Vp) of the third transistor M3. Whereas Vp is a higher voltage, the voltage of data line will be a lower voltage. After that, the inverse data is then written back onto Vp via the first transistor M1 in the writing period. Finally, Vp is coupled by the scan signal through the storage capacitance (CS) and held until the next operation period. The refresh operation must be performed row by row so the largest power is consumed in pre-charging of the data line. For multi-bits applications, the static and dynamic digital MIP circuits still require many scan lines and capacitors to reach polarity inversion.
Therefore, the adoption of analog concept for MIP circuit is attempted since it can achieve high image quality with fewer components. However, the output voltage of the analog memory circuit may have inaccuracy with corresponding data signal, which means that the static image may be distorted by the asymmetric inversion voltage.
Therefore, at present it requires an analog memory cell circuit to minimize the refresh frequency of static image, and reduce the asymmetric inversion voltage to achieve symmetric output waveform. Moreover, a compensation technique is implemented to improve the threshold voltage drop on the output from the input data.